for the drug known as Phy Methadone Unreferenced date July 2009 PHY is an abbreviation for the physical layer of the OSI model . An instantiation of PHY connects a link layer device often called a Media Access Control MAC to a physical medium such as an optical fiber or copper cable . A PHY device typically includes a Physical Coding Sublayer PCS and a Physical Medium Dependent PMD layer. The PCS encodes and decodes the data that is transmitted and received. The purpose of the encoding is to make it easier for the receiver to recover the signal. Example uses Wi Fi The PHY portion consists of the RF, mixed signal and analog portions, that are often called transceivers, and the digital baseband portion that place high demand on the digital signal processing DSP and communication algorithm processing, including channel code s. It is common that these PHY portions are integrated with the media access control MAC layer in System on a chip SOC implementations. Other similar wireless applications are 3G 4G 3GPP Long Term Evolution LTE , WiMAX , UWB etc. Ethernet A PHY chip PHYceiver is commonly found on Ethernet devices. Its purpose is physical, analog signal access to the link. It is usually used in conjunction with an Media Independent Interface MII chip or interfaced to a microcontroller that takes care of the higher layer functions. Universal Serial Bus USB A PHY chip is integrated ... like the VIA Technologies VT6421 use a PHY. SDRAM chip interfaces Flash memory chip interfaces ... booting Boot ROM functionality is implemented in the network interface card NIC , which may have PHY ... line speeds is implemented with Digital signal processor DSP inside the ethernet PHY. Some examples ... VIA6103. External links http netwinder.osuosl.org pub netwinder docs nw PHY 1890.pdf osuosl.org ICS1890 10Base T 100Base TX Integrated PHYceiver datasheet DEFAULTSORT Phy Category Physical layer protocols Category Integrated circuits compu hardware stub de PHY fr PHY pt PHY zh PHY ... more details
Pro Phy Lac Tic Brush Company was a health care business established in 1866. Makers of a highly advertised Pro phy lac tic toothbrush ref name brush , it was acquired by the Lambert Pharmaceutical Co. on February 19, 1930. ref Lambert s 1930 Sales 14 Under 1930 Record , Wall Street Journal , March 29, 1930, pg. 1. ref Based in Florence, Massachusetts , the firm was first called the Florence Manufacturing Company. Its name was changed on September 15, ref name dental Prophylactic Brush , Wall Street Journal, October 8, 1924, pg. 13. ref 1924. ref name brush Pro phy lac tic Brush Co., Wall Street Journal, September 3, 1924, pg. 3. ref From 1887 1924 the corporation paid a regular dividend on its common stock . ref name dental During World War II the company manufactured dummy plastic bayonets for the USN Mk 1 Dummy Training Rifle for the U.S. Navy. ref http www.usmilitaryknives.com knife knotes 9.htm ref References references Category Defunct companies based in Massachusetts Pro Phy Lac Tic Brush Company Category Dental companies Pro Phy Lac Tic Brush Company Category 1866 establishments Pro Phy Lac Tic Brush Company Category Companies disestablished in 1930 Pro Phy Lac Tic Brush Company US manufacturing company stub ... more details
Management Data Input Output, or MDIO , is a serial bus defined for the Ethernet IEEE 802.3 specification for Media Independent Interface , or MII . The MII connects Media Access Control MAC devices with PHY physical bus interface , or PHY, circuits. The MII comprises a data interface to the Ethernet link and a management interface, referred as MDIO or as Media Independent Interface Management MIIM . The MDIO bus provides access to the configuration & status registers of each PHY. These registers are used to initially configure each PHY and also to monitor status during operation. TOC Electrical specification The MDIO interface is implemented by two lines a MDC clock line and an MDIO data line The clock line is driven by the MAC device. The data line is bidirectional the PHY drives it to provide register data at the end of a read operation. The bus has a single MAC master, but can have up to 31 PHY slaves. The MDC clock can be aperiodic, with a minimum period of 400 ns, which corresponds to a maximal frequency of 2.5 MHz. Newer chips, however, allow faster acesses. The MDIO data line has a pull up of 1.5 kOhm in the PHY, allowing the MAC to determine if one or more PHYs are attached. The MAC should have a 2 kOhm pull down on that same line. Bus timing Between two accesses, the MAC and the PHY can drive the MDIO line tri state. Before a register access, PHY devices generally require a preamble of 32 ones on the MDIO line. The accesses are made out of 16 control bits followed by 16 data bits. The control bits specify the access type read or write , the PHY address and the register address. File MDIO READ WRITE.jpg During a write command, the MAC provides control and data. In the case of a read command, the PHY takes over the bus at the end of the cycle and supplies the MAC with the data. Registers The Clause 22 MDIO interface specifies 5 PHY address bits which account for up to 32 devices and 5 register address bits which allows up to 32 ... more details
Cx4 may refer to The Beretta Cx4 Storm , a pistol caliber carbine. The Cx4 chip , a math coprocessor by Capcom. 10 Gigabit Ethernet 10GBASE CX4 10GBASE CX4 , a copper based 10 Gigabit Ethernet PHY disambig ... more details
RNase PhyM is a type of endoribonuclease which is sequence specific for single stranded RNAs. It cleaves 3 end of unpaired A and U residues. External links MeshName endoribonuclease Phy M cite journal author Donis Keller H title Phy M an RNase activity specific for U and A residues useful in RNA sequence analysis journal Nucleic Acids Res. volume 8 issue 14 pages 3133 42 year 1980 pmid 6160466 doi 10.1093 nar 8.14.3133 pmc 324360 Category Ribonucleases biochem stub ... more details
orphan date November 2009 General Purpose Serial Interface , also known as GPSI , 7 wire interface , or 7WS , is a 7 wire communications interface. It is used as an interface between Ethernet Media Access Control MAC and PHY blocks. Data is received and transmitted using separate data paths TXD, RXD and separate data clocks TXCLK, RXCLK . Other signals consist of transmit enable TXEN , receive carrier sense CRS , and collision COL . class wikitable GPSI Signals Signal Name Direction Description TXD MAC PHY Transmit Data driven on rising edge of TXCLK TXEN MAC PHY Transmit Data Enable indicates valid TXD ... etc ... ... ... See also Media Independent Interface MII Category Ethernet compu hardware stub ... more details
Infobox Airport name Phetchabun Airport nativename a lang th image IATA PHY ICAO VTPL type Public Military type Public owner operator Government city served Phetchabun , Thailand location elevation f 450 elevation m 137 coordinates coord 16 40 33 N 101 11 42 E region TH type airport website metric rwy Y r1 number 18 36 r1 length f 6,890 r1 length m 2,100 r1 surface Asphalt footnotes Source DAFIF ref name WAD WAD VTPB source DAFIF ref ref name GCM GCM PHY source DAFIF ref Phetchabun Airport lang th airport codes PHY VTPB is an airport serving Phetchabun lang th , a Provinces of Thailand province in northern Thailand . Airlines and destinations Airport dest list Solar Air Bangkok Don Mueang Begins 14 January , Loei Begins 14 January See also List of airports in Thailand References References External links NWS current VTPB ASN PHY Navigation box br Airports in Thailand Category Airports in Thailand Thailand struct stub Asia airport stub de Flughafen Phetchabun th vi S n bay Phetchabun ... more details
Orphan date February 2009 Cleanup rewrite date May 2009 Ingress cancellation is an advanced PHY chip PHY technology that digitally removes in channel ingress. If a carrier appears in the middle of the upstream data signal, ingress cancellation can remove the interfering carrier without causing packet loss. Ingress cancellation also removes one or more carriers that are higher in amplitude than the data signal. Ingress cancellation eventually will break if the in channel ingress gets too high. External links http www.cisco.com en US tech tk86 tk319 technologies white paper09186a0080231a71.shtml Cisco used the term when describing a product Comp eng stub Category Digital electronics Category Technology ... more details
of Ethernet physical layer transceivers PHY chip PHY to Ethernet switch networking switch es. It reduces the number of signals pins required for connecting to the PHY from 16 for an Media Independent ... major parts The Media Access Control MAC Media Access Controller , the PHY PHYsical Interface or transceiver ..., etc and the PHY handles the low level logic 4B 5B encoding decoding, SerDes SERDES serialization ... between the MAC and PHY others include MII and SNI, with additional wider interfaces including ... chip and in some cases the chip may have many other functions. One or more PHY interfaces may be on the same chip, particularly in Ethernet switches. Some MAC and PHY ICs support both MII and RMII. Usually, the MAC and PHY are on the same board for 10 100 Ethernet though for gigabit and higher pluggable PHY modules may be used to allow the use of different media including twisted pair and optical .... Signals TXD0 Transmit data bit 0 MAC to PHY transmitted first TXD1 Transmit data bit 1 MAC to PHY TX EN When high, clock data on TXD0 and TXD1 to the transmitter MAC to PHY RXD0 Receive data bit 0 PHY to MAC received first RXD1 Receive data bit 1 PHY to MAC CRS DV, Carrier Sense CRS RX Data Valid .... PHY to MAC RX ER Receive Error optional on switches PHY to MAC REF CLK Continuous 50 MHz Reference ... from MAC to PHY. MDIO Management data I O line IIC SMBus TWI compatible bidirectional, open drain MDC Management data clock line bidirectional but MAC to PHY in practice though perhaps the PHY can ... instead the two prescalers MAC and PHY operate asynchronously with respect to each other. There is no signal ... and the PHY need to agree. This is presumably handled by the MDIO MDC interface though things might get interesting if the PHY and switch renegotiate the link speed at an unexpected time perhaps after ... 3.3 V , not nowrap 5 V tolerant. Intel LXT9781 LXT9761 8 6 port PHY nowrap 5 V tolerant. Atmel AT91SAM7XC256 microcontroller nowrap 5 V tolerant, AMD 79C875 4 port PHY nowrap 5 V tolerant, FPGAs ... more details
Sublayer for transmit or the PHY for receive . The byte stream of each lane is 8b 10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 Baud GBaud . The XGXS at the PHY end of the XGMII Extender PHY XGXS and the XGXS at the RS end DTE XGXS may operate on independent ... and PHY device, and operates symmetrically with similar functions on the Data Terminal Equipment ... XAUI with the 10GBASE LX4 8b 10b PHY, where the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality required by the PHY. An XGXS layer is not required at the PHY ... on the XAUI in order to meet PHY jitter requirements. Specifications IEEE 802.3 Section 4 Chapter ... more details
Unreferenced date December 2009 MLME Stands for Media Access Control MAC Sublayer Management Entity. MLME is the management entity where the Physical layer PHY MAC state machines reside. Examples of states an MLME may assist in reaching Authenticate Deauthenticate Associate Disassociate Reassociate Beacon Probe Timing Synchronization Function TSF PLME On the other hand PLME stands for Physical Layer Management Entity. DEFAULTSORT Mlme Category Media Access Control ... more details
Gigabit Media Independent Interface GMII is an interface between the Media Access Control MAC device and the physical layer PHY . The interface defines speeds up to 1000 Mbit s, implemented using an eight bit data interface clocked at 125 MHz, and is backwards compatible with the Media Independent Interface MII specification. It can also operate on fall back speeds of 10 100 Mbit s as per the MII specification. Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check CRC checksum. The GMII interface is defined in IEEE Standard 802.3, 2000 Edition http ieeexplore.ieee.org xpl standardstoc.jsp?isnumber 19017 Transmitter GTXCLK clock signal for gigabit TX.. signals 125 MHz TXCLK clock signal for 10 100 Mbit signals TXD 7..0 data to be transmitted TXEN transmitter enable TXER transmitter error used to corrupt a packet Notes on transmit clocks There are two clocks, depending on whether the PHY is operating at gigabit or 10 100 Mb speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10 100 Mb the TXCLK supplied by PHY is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit s or 2.5 MHz for 10 Mbit s connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent. Receiver RXCLK received clock signal recovered from incoming received data RXD 7..0 received data RXDV signifies data received is valid RXER signifies data received has errors COL Collision Detect half duplex connections only CS Carrier Sense half duplex connections only Management MDC Management interface clock MDIO Management interface I O bidirectional pin. The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits. The firs ... more details
nofootnotes date September 2010 Active State Power Management or ASPM is a power management protocol used to manage PCI Express based serial link devices as links become less active over time. It is normally used on laptop s and other mobile Internet device s to extend battery life. Action As Serial communication serial based PCIe bus devices, such as IEEE 1394 interface IEEE1394 FireWire , become less active, it is possible for the computer s power management system to take the opportunity to reduce overall power consumption by placing the link PHY chip PHY into a low power mode and instructing other devices on the link to follow suit. This is usually managed by the operating system s power management software or through the BIOS , thus different settings can be configured for laptop battery mode versus running from the battery charger . Low power mode is often achieved by reducing or even stopping the serial bus clock as well as possibly powering down the PHY chip PHY device itself. While ASPM brings a reduction in power consumption, it can also result in increased Latency engineering latency as the serial bus needs to be woken up from low power mode, possibly reconfigured and the host to device link re established. This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs. This may be acceptable for mobile computing, however, when battery life is critical. Currently, two low power modes are specified by the PCIe 2.0 specification L0s and L1 mode. The first mode concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. The second mode, L1, is bidirectional and results in greater power reductions though with the penalty of greater exit latency. See also Energy Star Green computing External links http www.pcisig.com specifications pciexpress specifications PCI Express Specifications PCI SIG http www.pcisig.com specifications pciexp ... more details
retrieved on 15 10 2010 ref Basic Mode Configuration 0 Status Word 1 PHY Identification 2, 3 Ability ... begins with sync bits before the data payload. At powerup the PHY usually adapts to whatever ... more details
networks WLAN . Task group 3 High Rate WPAN 3 High Rate WPAN IEEE 802.15.3 2003 is a MAC and PHY standard for high rate 11 to 55 Mbit s WPANs. 3a WPAN High Rate Alternative PHY IEEE 802.15.3a was an attempt to provide a higher speed Ultra wideband UWB PHY enhancement amendment to IEEE 802.15.3 for applications ... Millimeter Wave Alternative PHY 802.15.3c 2009 was published on September 11, 2009. The task group TG3c developed a millimeter wave based alternative physical layer PHY for the existing 802.15.3 Wireless ... IEEE 802.15.5, ZigBee , 6LoWPAN , WirelessHART , and ISA100.11a . 4a WPAN Low Rate Alternative PHY ... groups 802 15 pub TG4a.html IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a TG4a ... 2006 and was published in September 2006 as IEEE 802.15.4 2006. 4c PHY Amendment for China The IEEE 802.15 Task Group 4c is defining a PHY amendment which, when published, will be additive to both the IEEE Std 802.15.4 2006 standard and the IEEE Std 802.15.4a 2007 amendment. This PHY amendment is to address ... in January 2009. 4d PHY and MAC Amendment for Japan The IEEE 802.15 Task Group 4d is chartered ... be limited to defining a new PHY and such changes to the MAC as are necessary to support a new frequency ... compatibility with modifications being proposed within the Chinese WPAN. 4f PHY and MAC Amendment ... Physical PHY layer s and enhancements to the 802.15.4 2006 standard MAC layer which are required to support new PHY s for Active RFID System bi directional and location determination applications. 4g PHY Amendment for Smart Utility Network IEEE 802.15.4g Smart Utility Networks SUN Task Group is chartered to create a PHY amendment to 802.15.4 to provide a global standard that facilitates very large ... year 2011 pages 1 6 ref Task group 7 VLC This Task Group is chartered to write a PHY and MAC standard ... more details
Galli et al., IEEE Communications Magazine, July 2008 , provides an overview of P1901 PHY MAC proposal ... a potential ITU T G.hn Compatible PHY MAC option subsequently removed , and TSG4 is in charge ... more details
Layer is split into two sublayers Layer 1 the actual physical layer and Layer 1.5 the PHY Adapter ... layer is a separate specification as the various PHY options are reused ref http www.mipi.org specifications Overview of MIPI specifications , D PHY is used in the DSI, CSI, and UniPro specifications, M PHY is used in the UniPro, DigRFv4 and LLI specifications ref in other Mobile Industry Processor ... color white align center Layer 1.5 align center PHY adapter Physical layer abstraction and multi ... Layer 1 align center Physical layer PHY Signaling, clocking, line encoding, power modes align center PHY symbol The UniPro specification itself covers Layers 1.5, 2, 3, 4 and the DME Device Management ... the PHY to be reused by other less generic protocols if needed. OSI Layers 5 Session and 6 Presentation are, where applicable, counted as part of the Application Layer. Physical Layer L1 D PHY Versions 1.0 and 1.1 of UniPro use MIPI s D PHY technology for the off chip Physical Layer. This PHY allows inter chip communication. Data rates of the D PHY are variable, but are in the range of 500 1000 Mbit s lower speeds are supported, but at decreased power efficiency . The D PHY was named after the Roman number for 500 D . The D PHY ref https members.mipi.org mipi adopters file fix Specifications Board 20Approved mipi D PHY specification v01 00 00.pdf MIPI Alliance Specification for D PHY v1.00.00 ,requires an account at the MIPI website ref uses differential signaling to convey PHY symbols ... signal from the source to the destination. The D PHY technology thus uses a total of 2 clock wires per direction plus 2 signal wires per lane and per direction. For example a D PHY might use 2 wires ... directions are totally independent at this level of the protocol stack. In UniPro, the D PHY is used ... this to represent special control symbols outside the usual 0 to 255 values . The PHY itself uses this to represent certain special symbols that have meaning to the PHY itself e.g. IDLE symbols . Note ... more details
PHY interface definitions PL 3 and PL 4 which themselves came from the ATM Forum s Utopia definitions ... or SPI as it is widely known is a protocol for packet and cell transfers between PHY and LINK layer ... usage of SPI interface is in connecting Network Processors to PHY layer devices. ie. connecting the MSF of IXP2800 LINK layer with IXF framer PHY layer . Example GigEth SPI Network Processor Technical .... SPI 4.2 supports a data width of 16 bits and can be PHY link, link link, link PHY or PHYPHY ... more details
Teridian Semiconductor or TSC is a fabless semiconductor company designing and selling mixed signal ICs, located in Irvine, California . Products Teridian is a fabless semiconductor company specializing in analog mixed signal products and is focused on developing system on chip SOC solutions for energy metering, measurement, control and communications which enable the Smart Grid . It also provides 10 100 Ethernet PHY, MAC PHY, SFP Modules, VOIP FXO, PSTN soft modems with silicon DAA, smart card interface and secure access controllers. Brief history Teridian, commonly abbreviated TSC, was formed on April 8, 2005 in a leveraged buyout arranged by Golden Gate Capital, a venture capital firm. TSC is the former semiconductor division of TDK Corporation . Earlier, TSC was part of Silicon Systems Inc. of Tustin, California . References references External links http www.teridian.com Teridian s Web Site Category Electronics companies of the United States Category Fabless semiconductor companies Category Companies based in Irvine, California ... more details
Infobox University name Universidad An huac M xico Sur image Image Logouas.jpg center motto Vince in Bono Malum Defeat Evil with Good established 1981 type Private university president Dr. Jorge L pez Gonz lez city Mexico City state Federal District Mexico D.F. country Mexico undergrad postgrad Fraternities Phy Delta Phy Law Faculty campus Urban area Urban free label Students mascot Black Lion free 2,000 website http www.uas.mx Official The Universidad An huac M xico Sur was founded in 1981 in the southern part of Mexico City . The university overlooks the city, volcanoes and the top of Cumbres del Ajusco National Park . The An huac is part of more than 100 educational institutions worldwide that were founded by Father Marcial Maciel . coord missing Mexico DEFAULTSORT Universidad Anahuac Del Sur Category Educational institutions established in 1981 Category Roman Catholic universities and colleges in Mexico Category Universities in Mexico City Anahuac del Sur Category Consortium for North American Higher Education Collaboration Mexico edu stub es Universidad An huac del Sur ... more details
DFI may refer to DFI , or Diamond Flower Inc. or slogan Design For Innovation , is a major motherboard manufacturer based in Taiwan. Deep Flow Inspection , which is related to Deep Packet Inspection DDR PHY Interface , an interface protocol between memory controller logic and PHY interfaces Depository institution Depository Financial Institution Design For Industry DFI , the Leading Bank Merchandiser in the United States Development Finance Institution Divine Feminine Institute , alternative education in Tantra, Taoism and Spiritual Psychology Deutsch Franz sisches Institut , a French language institute in Erlangen Deep Foundations Institute , a non profit technical association in deep foundation construction Digital Freedom Initiative Gasoline direct injection Direct Fuel Injection Department of Financial Institutions Doha Film Institute , an umbrella organisation bringing all of Qatar s various film initiatives under a single banner. Dunedin Fashion Incubator Differential Fluorescence Induction Development Fund for Iraq Direct Foreign Investment Foreign direct investment Dr bak Frogn IL disambig da DFI de DFI fr DFI it DFI ... more details
Merge Torricelli s law date March 2010 File Spouting can jets.svg frame right A diagram of the spouting can experiment. is labelled, the pressure increases with depth. The spouting can experiment is a physics experiment designed to show that, according to Torricelli s Law , in a liquid with an open surface, pressure increases with depth. It consists of a tube with three separate holes in and an open surface. The three holes are blocked, then the tube is filled with water. When it is completely full, the holes are unblocked. The jets become more powerful and travel a larger distance the further down the tube they are. ref http www.4physics.com phy demo SpoutingCylinder SpoutingCylinder.html Spouting cylinder fluid flow Bot generated title ref Ignoring viscosity and other losses, if the nozzles point vertically upward then each jet will reach the height of the surface of the liquid in the container. See also Fluid dynamics References reflist External links http www.4physics.com phy demo SpoutingCylinder SpoutingCylinder.html Article on Spouting Cylinder Category Physics experiments ... more details
Orphan date February 2009 Notability date December 2008 Wisconsin Hills Middle School is a Middle School located in Brookfield, Wisconsin . coord missing Wisconsin Category Middle schools in Wisconsin Wisconsin school stub it is separated in 6 alpha, 6 beta, 6 gamma, 7 alpha, 7 beta, 7 gamma, 8 alpha, 8 beta and 8 gamma. the number represents your grade. 6 alpha Bergmann Radomski Adkinson Dentice 6 Beta Green Geyser 6 Gamma O reagan Engel Sanders Gorace 7 Beta Nigle Schaefer Kanies Phy Ed Teachers Scroble Gufsufson Principal Martino Vice Principal Shoulteck ... more details
PL 3 or POS PHY Level 3 was the name of the interface that the Optical Internetworking Forum s SPI 3 Interoperability Agreement is based on. It was proposed by PMC Sierra to the Optical Internetworking Forum and adopted in June of 2000 . The name means Packet Over SONET Physical layer level 3. PL 3 was developed by PMC Sierra in conjunction with the SATURN Development Group . Context There are two broad categories of chip to chip interfaces. The first, exemplified by PCI Express and HyperTransport , supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interface s and the Optical Internetworking Forum family of System Packet Interface s. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet oriented, chip to chip interface family used between devices in the Packet over SONET and Optical Transport Network , which are the principal protocols used to carry the internet between cities. Applications It was designed to be used in systems that support OC 48 SONET interfaces . A typical application of PL 3 SPI 3 is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace. Technical details The interface consists of per direction 32 TTL signals for the data path 8 TTL signals for control one TTL signal for clock 8 TTL signals for optional additional multi channel status There are several clocking options. The interface operates around 100 MHz. Implementations of SPI 3 PL 3 have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets. Trivia The name is an acronym of an acronym of an acronym as the P in PL stands for POS PHY and the S in POS PHY stands for SONET Synchronous Optical Network . The L in PL ... more details
Reduced Gigabit Media Independent Interface RGMII specifies a particular interface between an Ethernet Media Access Control MAC and PHY chip Ethernet PHYceiver PHY . RGMII uses half the number of data pins as used in the Gigabit Media Independent Interface GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit s operation, and by eliminating non essential signals carrier sense and collision indication . Thus RGMII consists only of RX CTL, RXC, RXD 3 0 , TX CTL, TXC, TXD 3 0 12 pins, as opposed to GMII s 24 . Ie FrameStart BitClock Data. Unlike Media Independent Interface MII , the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10 100 Mbit s operation and by the MAC at 1000 Mbit s. RGMII supports Ethernet speeds of class wikitable & 91 Mbit s& 93 & 91 Hertz MHz & 93 Bits Clockcycle align right 10 align right 2.5 align right 4 align right 100 align right 25 align right 4 align right 1000 align right 125 align right 8 See also Media Independent Interface MII Reduced Media Independent Interface RMII Gigabit Media Independent Interface GMII Serial Gigabit Media Independent Interface SGMII References http www.hp.com rnd pdfs RGMIIv2 0 final hp.pdf hp.com RGMIIv2 0 final hp.pdf RGMII 2002 04 01 Version 2.0 compu network stub Category Ethernet ru RGMII ... more details
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