Diagram of the computer memory hierarchy

Most modern CPUs are so fast that for most program workloads, the locality of reference of memory accesses and the efficiency of the caching and memory transfer between different levels of the hierarchy are the practical limitation on processing speed. As a result, the CPU spends much of its time idling, waiting for memory I/O to complete.

The memory hierarchy in most computers is:

• Processor registers – fastest possible access (usually 1 CPU cycle), only hundreds of bytes in size
• Level 1 (L1) cache – often accessed in just a few cycles, usually tens of kilobytes
• Level 2 (L2) cache – higher latency than L1 by 2× to 10×, often 512 KiB or more
• Main memory (DRAM) – may take hundreds of cycles, but can be multiple gigabytes. Access times may not be uniform, in the case of a NUMA machine.
• Disk storage – millions of cycles latency, but very large
• Tertiary storage – several seconds latency, can be huge

The various major units in a typical memory system can be viewed as forming a hierarchy of memories (m₁,m₂,...,m_n) in which each member m_i is in a sense subordinate to the next highest member m_i-1 of the hierarchy.

Management

Modern programming languages mainly assume two levels of memory, main memory and disk storage, though in assembly language, and in inline assembler in languages such as C, registers can be directly accessed. Taking optimal advantage of the memory hierarchy requires the cooperation of programmers, hardware, and compilers (as well as underlying support from the operating system):

• Programmers are responsible for moving data between disk and memory through file I/O.
• Hardware is responsible for moving data between memory and caches.
• Optimizing compilers are responsible for generating code that, when executed, will cause the hardware to use caches and registers efficiently.

See also

• Virtual memory

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