In computer microprocessor architecture, a back side bus (BSB), or backside bus, is a computer bus used to connect the CPU to CPU cache memory, usually L2. If a design utilizes it along with a front side bus (FSB), it is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB)^[1] architecture.

BSB is an improvement over the older practice of accessing the cache over the front side bus (FSB), because FSB is typically a severe bottleneck in modern systems. In addition, due to its dedicated nature, the back side bus can be optimized or customized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose FSB. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.

Cache connected with a BSB was initially external to the CPU silicon chip, but now is usually on-chip.^[2] In the latter case, the BSB clocking frequency is typically equal to the processor's, and the back side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.

The dual-bus architecture has been used in a number of chips, including the IBM and Freescale PowerPC processors (certain PowerPC 604 models, the G3 line based on the PowerPC 750^[3], and the Freescale G4 line), as well as the Intel Pentium Pro and Pentium II processors^[4], which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).

See also

• CPU cache
• Computer bus
• Front side bus

References

1. ↑
2. ↑
3. ↑
4. ↑